--
-- VHDL Architecture fft_lib.stages.arch
--
-- Created:
--          by - andax656.student (southfork-15.edu.isy.liu.se)
--          at - 10:54:49 10/24/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY stages IS
   GENERIC( 
      s : integer
   );
   PORT( 
      enable_stages : IN     std_logic;
      fpga_clk      : IN     std_logic;
      fpga_reset_n  : IN     std_logic;
      data_im       : INOUT  integer RANGE 8388607 DOWNTO -8388608;
      data_re       : INOUT  integer RANGE 8388607 DOWNTO -8388608
   );

-- Declarations

END stages ;

--
ARCHITECTURE arch OF stages IS
BEGIN
END ARCHITECTURE arch;

